LOT: Logic Optimization with Testability - new transformations for logic synthesis

A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

Buffer assignment algorithms for data driven architectures

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references.Data driven architectures designed to achieve high performance and throughput require the corresponding data flow graph to have no accumulation of data at its nodes and simultaneous arrival of all input data to a multi-input node. Buffers are therefore inserted to ensure these conditions. An algorithm for buffer distribution in a balanced Data Flow Graph, DFG is proposed. The number of buffers in the proposed buffer distribution strategy is equal to the minimum number of buffers as achieved by integer programming techniques. We also propose an extension of this algorithm which can further reduce the number of buffers by altering the DFG while keeping the functionality and performance of the DFG intact. The time complexities of the proposed algorithms have been shown to be O(V x E) and O(V'xlogV) re spectively; an improvement over the existing strategies. A novel buffer distribution algorithm to maximize the pipelining and throughput has also been proposed. The number of buffers obtained by this algorithm is substantially less than the existing schemes and can be effectively applied to data driven architectures with large node sizes. Performance results indicate that the proposed strategies outperform all the existing strategies in terms of the number of buffers, while possessing the lowest time complexities

LOT: Logic optimization with testability - New Transformations using recursive learning," ICCAD

Abstract: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pattern testability. The method isbased on structural transformations at the gate level. New transformations involving EX-OR gates derived based on indirect implications by Recursive Learning have been introduced in the synthesis of multi-level circuits. This method is augmented with transformations that speci cally enhance randompattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology can not only realize lower area, but also achieves better testability compared to testability enhancement synthesis tools such as tstfx. Speci cally for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations can yield smaller circuits compared to state-of-the-art logic optimization tools like SIS and HANNIBAL.